1. Field of the Invention
The present invention relates to plasma display panels (PDPs), and more particularly, to an electronic waveform technique that minimizes vertical crosstalk in a PDP.
2. Background of the Art
Color PDPs are well known. FIG. 1 illustrates a prior art embodiment of a color alternating current (AC) PDP, as disclosed in U.S. Pat. No. 6,118,214 to Marcotte (hereinafter xe2x80x9cthe Marcotte ""214 patentxe2x80x9d), which is incorporated herein by reference. Transparent electrodes 11 are employed on a front panel. A front plate (not shown) includes horizontal plural pairs of sustain electrodes 10 that connect transparent electrodes 11 to a sustain bus 12. A plurality of pairs of scan electrodes 14 are juxtaposed to paired sustain electrodes 10, and both electrode sets are covered by a dielectric layer (not shown) and a magnesium oxide (MgO) layer (not shown). A back plate (not shown) supports vertical barrier ribs 16 and plural vertical column electrodes 18 (shown in phantom). Individual column electrodes 18 are covered with red, green, or blue (RGB) phosphors, as the case may be, to enable a full color display to be achieved. The front and rear plates are sealed together and a space therebetween is filled with a dischargeable gas.
An electrode pair is defined as (a) a sustain electrode 10 (and its adjacent transparent electrode 11) juxtaposed with (b) a scan electrode 14 (and its adjacent transparent electrode 11). A pixel 20 is defined as an area that includes intersections of (i) an electrode pair of sustain electrode 10 and scan electrode 14 on the front panel, and (ii) three column electrodes 18 for red, green, and blue, respectively, on the back panel. A subpixel corresponds to an intersection of a red, green or blue column electrode with an electrode pair of a sustain electrode and a scan electrode. For example, subpixel 19 corresponds to an intersection of a red column electrode 18 with an electrode pair of sustain electrode 10 and scan electrode 14.
Operating voltage and power of the PDP are controlled by a discharge gap 13 and a width of transparent electrode 11. The operating voltage of the PDP is controlled by the distance across the discharge gap 13, as the distance controls the breakdown voltage for a given gas mixture. Furthermore, sufficient voltage must be applied so that the ensuing gas discharge plasma is able to fully engulf the scan and sustain electrode pair. The power consumed by the discharge is affected by the surface capacitance of the electrode pair, which is proportional to electrode area and inversely proportional to the dielectric thickness.
A width of sustain electrode 10 and a width of scan electrode 14 are chosen to produce a narrow discharge gap 13 and a wide inter-pixel gap 15. When sufficient voltage is applied across discharge gap 13, the gas will break down forming a discharge plasma. For a given applied voltage, the positively charged electrode is the anode and the negatively charged electrode is the cathode. The discharge plasma has two distinct regions, the positive column and the negative glow. The positive column consists predominantly of fast moving electrons seeking the positive charge on the surface of the anode electrode. Conversely, the negative glow contains slow moving ions drifting toward and across the negatively charged cathode electrode. The duration of the discharge is limited by the amount of charge on the dielectric surfaces. Once the charge has been neutralized the discharge self-extinguishes. Within a sustain time period, this process is repeated by alternating the voltage polarity after each discharge completes. Inter-pixel gap 15 must be made sufficiently large to prevent the energetic positive column of the plasma discharge from bridging the inter-pixel gap and corrupting an ON or OFF state of an adjacent pixel. The width of the transparent electrode 11 and the thickness of a dielectric glass (not shown) over the electrode determine the pixel""s discharge capacitance, which controls the discharge power and therefore brightness. For a given discharge power/brightness, a number of discharges is chosen within sustain time periods to provide gray scales which sum to meet the overall brightness requirement for the panel.
FIG. 2 shows a typical prior art block diagram of a PDP system 200. An analog video signal is input into logic 230 where the signal is digitized, processed, and temporarily stored. Once a frame""s worth of data is stored, logic 230 begins a process of displaying data through a series of subfields, typically 8 to 12, as disclosed in U.S. Pat. No. 5,724,054 to Shinoda.
FIG. 3 is a graph showing a division of a frame time into 8 subfields (i.e., SF1-SF8). During each addressing period lines Y1 through Y480 are scanned sequentially by row drivers 210, while video input is applied through column drivers 225 to set each sub-pixel in the ON state as required by the video input. Each subsequent sustain period is weighted with sustain pulses to achieve weighted light intensities for each subfield.
FIG. 4 shows a typical division of a subfield. Each subfield has a setup period, an addressing period, and a sustain period. The setup period turns off any ON pixels, primes the MgO layer, and sets up all the pixels for addressing. Referring to both FIG. 2 and FIG. 4, during the addressing period, a scan generator 205, in conjunction with row drivers 210, sequentially drives each row low for addressing. Once a given row is enabled, logic 230 loads column drivers 225 with image data corresponding to individual RGB sub-pixels requiring illumination based upon received image data. Column drivers 225 apply voltage Vx to selected column electrodes. The coincidence of a selected row and an applied column voltage initiates a weak discharge that cascades into a discharge between the selected scan electrode and its neighboring sustain electrode. Once completed, the discharge has placed the addressed sub-pixel in the ON state. Any column not driven will remain in the OFF state. While the addressing discharge does produce visible light, it is not of sufficient brightness to represent the image properly. Consequently, a sustain period follows the addressing period after the last row has been addressed. During the sustain period, scan generator 205 and a sustain generator 220 supply alternating sustain pulses so that a momentary ac-plasma discharge occurs on an application of each pulse. Each sustain discharge produces ultra violet light the excites surrounding phosphor to produce visible light. Each subfield within a frame contains a sufficient number of sustain pulses and in-turn discharges to achieve a desired brightness for each subfield. Since each sub-pixel can be addressed independently in each subfield, a large color palate is obtainable.
FIG. 5a shows a prior art composite waveform between the scan and sustain electrodes. Due to a capacitive relationship of the scan and sustain electrodes, the composite waveform is simply an output of scan generator 205 (FIG. 4 Scan waveform), minus an output of sustain generator 220 (FIG. 4 Sustain waveform). Note that applied data pulses are not included in FIG. 5a. 
FIGS. 5b-5e show wall voltage waveforms for each pixel addressing sequence. A wall voltage is an AC coupled voltage present on a gas side of a dielectric layer. The wall voltage is limited, positive and negative, by a breakdown voltage of the gas, Vbr and xe2x88x92Vbr.
When the breakdown voltage is exceeded in either direction, two types of discharges can occur, a well-known negative resistance discharge and a more recently discovered positive resistance discharge. According to U.S. Pat. No. 5,745,086 to Weber, and referring to FIG. 4, if an applied waveform rises or falls slowly, as in rising and falling ramps of the setup period t12 and t15, the gas will discharge having a positive resistance characteristic, behaving much like a zener diode limiting the voltage across the gas to the breakdown voltage Vbr. If the applied voltage exceeds the breakdown voltage sharply, as in the sustain periods t23, t24, a negative resistance or avalanche discharge occurs, which reduces the wall voltage to zero. Once the wall voltage reaches zero, the discharge self extinguishes.
The addressing discharge is also a negative resistance discharge, exhibiting the characteristics of a positive column discharge as disclosed in U.S. Pat. No. 6,184,848 to Weber (hereinafter xe2x80x9cthe Weber ""848 patentxe2x80x9d). The Weber ""848 patent defines the positive column discharge as having a trigger cell and a state cell. A panel topology is similar to that of FIG. 1, but less transparent electrodes 11 thereby creating a large discharge gap. In the presence of a high wall voltage, due to an application of sustain pulses following an addressing operation, a weak discharge forms between a positively charged back plate electrode and a negatively charged front electrode. This intersection is said to be a trigger cell. The weak discharge, in conjunction with the high wall voltage, yields a discharge where the plasma forms two clearly distinct regions, a negative glow and a positive column. The negative glow consists of slow moving positively charged ions, and the positive column consists of slow moving ions and rapidly moving electrons. The electrons move toward the positively charged anode, and the ions drift slowly toward the negatively charged cathode. As the weak discharge strengthens, the negative glow expands about the trigger cell, and the positive column spreads along the back plate""s phosphor layer to the positively charged state cell. The discharge completes when the charge is neutralized between the trigger cell and the state cell.
For the addressing discharge, the intersection of the column electrode and the selected scan electrode forms the trigger cell, and the corresponding sustain electrode intersecting with the same column electrode forms the state cell. At the completion of the setup period t16, each pixel is setup so that wall voltage is at the discharge level xe2x88x92Vbr. When the pixel is addressed, a weak discharge forms at the intersection of the selected scan electrode and at each of the driven back plate column electrodes. The discharge develops producing a positive column which spreads along the positively charged back plate electrode to the positively charged sustain electrode. The discharge then consumes the charge on the sustain electrode, reducing the wall voltage to zero.
FIG. 5b shows wall voltages for a previously OFF pixel, which is setup for addressing, not addressed, and remains OFF in a latter sustain period. Specifically, a rising ramp t12 in a setup period rises, bringing the wall voltage above the breakdown voltage and clamps the wall voltage at Vbr. Voltage Ve being applied at t13, as shown in FIG. 4, ensures that an address discharge will be strong enough for a first sustain discharge to occur properly. Increasing voltage Ve effectively makes the first sustain discharge stronger. A transition into the falling ramp t13 and t14 reverses the wall voltage and the falling ramp t15 clamps the wall voltage at xe2x88x92Vbr. At the conclusion of the setup period, the wall voltage is at xe2x88x92Vbr. A row select pulse at time t17 in FIG. 4 exceeds the breakdown voltage slightly due to a difference between Vrf and 0V. Since the falling ramp during time t15 stops at Vrf above 0V, a small negative voltage is effectively applied when the row select pulse is applied at time t17 to exceed the breakdown voltage xe2x80x94Vbr. Since this effective negative voltage, caused by Vrf is small and the width of the row select pulse at t17 is narrow, no discharge activity occurs unless there is a video input dictated data pulse on a data electrode coincident with the row select pulse at time t17 as shown in FIG. 4. In FIG. 5b, no data pulse is applied, and so there is no discharge activity at time t17. Since an address discharge did not occur, the wall voltage produced by the first sustain pulse at t21 is not greater the positive breakdown voltage Vbr and no sustain discharge will occur.
FIG. 5c shows the turn-on process for an OFF pixel. The setup period occurs as in FIG. 5b and a data pulse (not shown) is applied to the columns at time t17 triggering an address discharge which returns the wall voltage to zero. Later at time t21, after the remaining rows have been addressed, the first sustain discharge will occur on any pixel which was addressed. For the first sustain pulse, the scan electrode is driven high before lowering the sustain electrodes, unlike subsequent sustain pulses. This method of generating the first discharge prevents a premature discharge, which can form if the sustain electrode voltage of Ve, 220V is lowered before raising the scan electrode voltage to sustain voltage Vs, 180V, due to the application of voltage Ve in the setup period as shown in FIG. 4 during addressing. Having been addressed previously, the breakdown voltage Vbr is exceeded, and a negative resistance discharge will occur, again returning the wall voltage to zero. Each subsequent sustain pulse initiates another discharge producing the light of an ON pixel.
Following the first sustain discharge, the falling edge of the scan electrodes lowers the wall voltage towards the negative breakdown voltage xe2x88x92Vbr. The subsequent rise of the other sustain electrodes adds more voltage across the gas and exceeds the breakdown voltage xe2x88x92Vbr, producing the next discharge. This process continues for the duration of the sustain period with the discharges alternating back and forth.
FIG. 5d shows a re-addressing of an ON pixel. The application of the setup pulse at time t11 causes the last negative resistance discharge of the previous subfield""s sustain period. Since the wall voltage was returned to zero by the discharge, the rising ramp at t12 will not discharge since the rising wall voltage does not exceed Vbr. The falling ramp limits the wall voltage to xe2x88x92Vbr, as it did in FIGS. 5b and 5c. At time t17, a data pulse is applied with the row select, a discharge occurs, and the pixel is returned to the ON state.
FIG. 5e shows an ON pixel which is erased by the falling ramp t15 as in FIG. 5d, however it is not re-addressed, and is OFF in the latter sustain period.
As disclosed in the Marcotte ""214 patent, the paired front plate electrode configuration of FIG. 1 has the advantage of reduced inter-electrode capacitance, which reduces the power dissipation resulting from charging and discharging of the inter-electrode capacitance with each sustain pulse. However, there is an increased probability of vertical crosstalk. Vertical crosstalk occurs when a discharge at one discharge site spreads into a vertically adjacent discharge site. The Marcotte ""214 patent utilizes a large inter-pixel gap to help increase vertical pixel-to-pixel isolation. Note that the back plate barrier ribs provide horizontal pixel isolation but no vertical isolation. The greatest probability of crosstalk occurs during the addressing discharge where the plasma discharge forms between a selected scan and data electrodes and the positive column spreads to the sustain electrode.
FIG. 6 shows the time sequenced discharge mechanics for an address discharge showing crosstalk discharge. The pictorial is a cross sectional view the PDP of FIG. 1 showing front plate electrodes on top and orthogonally oriented address electrode on the bottom, which is covered by a phosphor layer. P1 refers to the red sub-pixel 19 of FIG. 1 and a vertically adjacent red sub-pixel, P2 with inter-pixel gap 15 separating P1 and P2. The time t0 for each row occurs with the application of the row select pulse at time t17 in conjunction with an applied data pulse to the address electrode. The sub-pixels were setup by the falling ramp applied to the scan electrodes while Ve was applied to the sustain electrodes. This places the negative charge on the scan electrodes and the positive charge on the sustain and back plate electrodes prior to t0. Vrf allows the row select pulse to slightly exceed the breakdown voltage to help speed up the address discharge. The application of voltage Vscan at time t16, in FIG. 4, by the row drivers 210, acts as a row deselect voltage by reducing the negative charge on the non-selected rows so that the wall voltage on the scan electrodes is reduced. This prevents the addressing of one row from affecting the other rows in the display. The full wall voltage returns at time t17 when the row is selected, and the breakdown voltage xe2x80x94Vbr is exceeded as shown in FIG. 5b. The Vscan voltage is a de-select voltage and must be high enough to ensure sufficient row to row isolation in the presence of applied column voltages.
If a data pulse is provided, at time t0 in FIG. 6 a weak discharge forms between the back plate address electrode and the active scan electrode, and at time t1, a negative resistance plasma discharge forms. At time t2, the availability of positive charge on the sustain electrodes allows the positive column to rapidly engulf the sustain electrode, and at time t3 can easily spread across the inter-pixel gap to the neighboring sustain electrode and thereby deplete the positive charge of the neighboring pixel P2. When P2""s scan electrode is selected and the column electrode is driven, the weak back to front discharge may form, however, without the positive charge on the sustain electrode, the plasma will not form, the scan electrode will maintain its negative charge, and pixel P2 will remain off.
In a paper entitled xe2x80x9cSymmetrically driven PDP, with minimized current loops to reduce EMIxe2x80x9d by Vossen et al. (hereinafter xe2x80x9cthe Vossen et al. paperxe2x80x9d), there is disclosed the usage of interlaced addressing to reduce crosstalk in a PDP. With interlaced addressing, the odd rows are addressed followed by the even rows. As such, any gas priming resulting from addressing the odd rows will be fully extinguished prior to addressing the even rows. The Vossen et al. paper also talks of a symmetrically sustained PDP that uses the paired electrode configuration described in the Marcotte ""214 patent as helping to reduce vertical crosstalk. However, the Vossen et al. paper does not describe or correct for the form of vertical crosstalk described herein. Specifically, the Vossen et al. paper describes addressing with the electrodes configured as non-paired electrodes (i.e., scan, sustain, scan, sustain), which does not have a common potential across an inter-pixel gap during addressing. In the non-paired case, a crosstalk discharge will in fact go in the wrong direction, discharging to an incorrect sustain electrode. The use of interlaced addressing reduces this likelihood of this artifact.
The present invention minimizes crosstalk discharge probability between pixels in a plasma display panel while retaining benefits of a paired electrode configuration. Also, an inter-pixel gap may be reduced to enlarge the pixel size to increase brightness, and the pixel density may be increased to realize a higher resolution display.
The present invention reduces probability of address discharge crosstalk in a paired electrode configuration by reducing voltage on an inactive sustain electrode during addressing. By reducing voltage on the inactive sustain electrode, a positive column formed in an address discharge will not spread across the inter-pixel gap. The sustain electrodes are separated into odd and even row associations. Operation of the setup and sustain cycles is unchanged. During addressing, the odd rows are addressed while the voltage on the even sustain electrodes is reduced. Once addressing of the odd rows is complete, the voltage on the even sustain electrodes is returned high, the voltage on the odd sustain electrodes is reduced, and the even rows are addressed.
In some embodiments of the present invention, the voltage on the inactive sustain electrodes is reduced only during the first half of addressing. In this case, crosstalk will continue to occur during the second half of addressing. However, this is acceptable since the crosstalk results in the inactive cell always being OFF during the sustain period.
The present invention may be applied to any paired electrode configuration independent of setup or sustain waveform variations, provided that the sustain electrodes are high while the scan electrodes are low during addressing, thus allowing for a discharge to form at the scan electrode, which then spreads to the sustain electrode, neutralizing the voltage therebetween.
The present invention a method for controlling sustain electrodes in a PDP. The method includes enabling a first sustain electrode to produce an addressing discharge, and disabling a second sustain electrode when the first sustain electrode is producing the addressing discharge. The first sustain electrode is adjacent to the second sustain electrode.
One embodiment of the invention is a circuit for controlling sustain electrodes in a PDP. The circuit includes an output for enabling a first sustain electrode to produce an addressing discharge, and an output for disabling a second sustain electrode when the first sustain electrode is producing the addressing discharge. The first sustain electrode is adjacent to the second sustain electrode.
Another embodiment of the present invention is a system that has a PDP having a first sustain electrode and a second sustain electrode adjacent to the first sustain electrode, and a circuit for (a) enabling the first sustain electrode to produce an addressing discharge, and (b) disabling the second sustain electrode when the first sustain electrode is producing the addressing discharge.